; even- or odd-number ed parity by uartcr1) are added to the transfer data. the transfer data formats are shown as follows. figure 10-2 tran sfer data format figure 10-3 caution on c hanging transfer data format note: in order to switch the transfer data format, perfor m transmit operations in the above figure 10-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 107 TMP86F409NG 10.4 transfer rate the baud rate of uart is set of uartcr1. th e example of the baud rate are shown as follows. when tc3 is used as the uart transfer rate (when uartcr1 = ?110?), the tr ansfer clock and transfer rate are determined as follows: transfer clock [hz] = tc3 source clock [hz] / ttreg3 setting value transfer rate [baud] = transfer clock [hz] / 16 10.5 data sampling method the uart receiver keeps sampling input using the cloc k selected by uartcr1 until a start bit is detected in rxd pin input. rt clock star ts detecting ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 10-4 data sampling method table 10-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
page 108 10. asynchronous serial interface (uart ) 10.6 stop bit length TMP86F409NG 10.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1. 10.7 parity set parity / no parity by uartcr1 and set parity type (odd- or even-numbered) by uartcr1. 10.8 transmit/receive operation 10.8.1 data transmit operation set uartcr1 to ?1?. read uartsr to check ua rtsr = ?1?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-cl ears uartsr, transfers the data to the transmit shift register and the data are sequenti ally output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if parity addition is specified. select the data transfer baud rate using uartcr1. when data transmit st arts, transmit buffer empty flag uartsr is set to ?1? a nd an inttxd interrupt is generated. while uartcr1 = ?0? and from when ?1? is written to uartcr1 to when send data are written to tdbuf, the txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transm it does not start. 10.8.2 data receive operation set uartcr1 to ?1?. when data are received vi a the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag ua rtsr is set and an intrxd interrupt is generated. select the data transfer baud rate using uartcr1. if an overrun error (oerr) occurs when data are received, the da ta are not transferre d to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting ua rtcr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 109 TMP86F409NG 10.9 status flag 10.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cl eared to ?0? when the rdbuf is read after read- ing the uartsr. figure 10-5 generati on of parity error 10.9.2 framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is r ead after reading the uartsr. figure 10-6 generati on of framing error 10.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read af ter reading the uartsr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears ferr.
page 110 10. asynchronous serial interface (uart ) 10.9 status flag TMP86F409NG figure 10-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr is cleared. 10.9.4 receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 10-8 generat ion of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun er ror flag which should have been cleared still remains set. 10.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf, uartsr is set to ?1?, that is, when data in tdbuf are transferred to the transmit shif t register and data transmit star ts, transmit data buffer empty flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the tdbuf is written after reading the uartsr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr intrxd interrupt rdbuf after reading uartsr then rdbuf clears rbfl.
page 111 TMP86F409NG figure 10-9 generation of transmit data buffer empty 10.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the data transmit is stated after writing the tdbuf. figure 10-10 generation of transmit end flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd pin uartsr inttxd interrupt after reading uartsr writing tdbuf clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr uartsr inttxd interrupt data write for tdbuf
page 112 10. asynchronous serial interface (uart ) 10.9 status flag TMP86F409NG
page 113 TMP86F409NG 11. serial expansion interface (sei) sei is one of the serial in terfaces incorporated in the TMP86F409NG. it allows connection to peripheral devices via full-duplex synchronous communication protocol s. the TMP86F409NG cont ain one channel of sei. sei is connected with an ex ternal device through sclk, mosi, miso and the terminal ss . sclk, mosi, miso, and ss pins respectively are shared with p02, p03, p04 and p05. when using these ports as sclk, mosi, miso, or ss pins, set the each port output latch to ?1?. 11.1 features ? the master outputs the shift clock for only a data transfer period. ? the clock polarity and phase are programmable. ? the data is 8 bits long. ? msb or lsb-first can be selected. ? the programmable data and clock timing of sei can be connected to almost all synchronous serial peripheral devices. refer to ?" 11.5 sei transfer formats "?. ? the transfer rate can be selected from the following four (master only): 4 mbps, 2 mbps, 1 mbps, or 250 kbps (when operating at 16 mhz) ? the error detection circuit su pports the following functions: a. write collision detection: when the shift register is accessed for write during transfer b. overflow detection: when new data is received wh ile the transfer-finished fl ag is set (slave only) note: mode fault detect function is not supported. make sure to set secr bit to "1" for disabling the mode fault detection. figure 11-1 sei (ser ial extended interface) sei control unit port control unit clock control unit shift register read buffer sei control register sei status register bit order selection clock selection 4, 8, 16, 64 divide miso mode mstr cpha cpol bos ser sef wcol sovf see mosi sclk ss sei data register address data sei interrupt (intsei1) internal sei clock
page 114 11. serial expansion interface (sei) 11.2 sei registers TMP86F409NG 11.2 sei registers the sei interface has the sei control register (secr), sei status register (sesr), and sei data register (sedr) which are used to set up the sei system and enable/dis able sei operation. 11.2.1 sei control register (secr) 11.2.1.1 transfer rate (1) master mode (transfer rate = fc/int ernal clock divide ratio (unit : bps)) the table below shows the relationship between settings of the ser bit and transfer bit rates when the sei is operating as the master. 76543210 secr (002ah) mode see bos mstr cpol cpha ser (initial value: 0000 0100) read-modify-write instruction are prohibited mode mode fault detection #1 #1 if mode fault detection is enabled, an interrupt is generated when the modf flag (sesr) is set. 0: enables mode fault detection 1: disables mode fault detection it is available in master mode only. (note: make sure to set bit to "1" for disabling mode fault detection r/w see sei operation #2 #2 sei operation can only be disabled after transfer is co mpleted. before the sei can be used, the each port control register and output latch control must be set for the sei function (in case p0 port, p0outcr and p0dr). when using the sei as the master, set the secr bit to ?1? (to enable sei operation) and then place transmit data in the sedr register. this initiates transmission/reception. 0: disables sei operation 1: enables sei operation bos bit order selection 0: transmitted beginning with the msb (bit 7) of sedr register 1: transmitted beginning with the lsb (bit 0) of sedr register mstr mode selection #3 #3 master/slave settings must be made before enabling sei operation (this means that the secr bit must first be set before setting the secr bit to ?1?). 0: sets sei for slave 1: sets sei for master cpol clock polarity 0: selects active-?h? clock. sclk remains ?l? when idle. 1: selects active-?l? clock. sclk remains ?h? when idle. cpha clock phase selects clock phase. for details, refer to section ?sei transfer for- mats?. ser selects sei transfer rate 00: divide-by-4 01: divide-by-8 10: divide-by-16 11: divide-by-64 table 11-1 sei transfer rate ser internal clock divide ratio of sei transfer rate when fc = 16 mhz 00 4 4 mbps 01 8 2 mbps 10 16 1 mbps 11 64 250 kbps
page 115 TMP86F409NG (2) slave mode when the sei is operating as a slave, the serial clock is input from the master and the setting of the ser bit has no effect. the maximum transfer rate is fc/4. note: take note of the following relationship betwe en the serial clock speed and fc on the master side: 15.625 kbps < transfer rate < fc/4 bps example) 15.625 kbps < transfer rate < 4 mbps (fc = 16 mhz at v dd = 4.5 to 5.5 v) 15.625 kbps < transfer rate < 2 mbps (fc = 8 mhz at v dd = 2.7 to 5.5 v) 11.2.2 sei status register (sesr) 11.2.3 sei data register (sedr) the sei data register (sedr) is used to send and receive data. when the sei is set for master, data transfer is initiated by writing to this sedr register. if the ma ster device needs to write to the sedr register after transfer began, always check to s ee by means of an interrupt or by polling that the sef flag (sesr) is set, before writing to the sedr register. 76543210 sesr (0028h) sef wcol sovf ?
page 116 11. serial expansion interface (sei) 11.3 sei operation TMP86F409NG 11.3 sei operation during a sei transfer, data transmissi on (serial shift-out) and reception (serial shift-in ) are performed simulta- neously. the serial clock synchronizes the timing at which information on the two serial data lines are shifted or sampled. slave device can be selected in dividually using the slave select pin ( ss pin). for unselected slave devices, data on the sei bus cannot be taken in. when operating as the master devices, the ss pin can be used to indicate multiple-master bus connection. 11.3.1 controlling sei clock polarity and phase the sei clock allows its phase and po larity to be selected in software from four combinations available by using two bits, cpha and cpol (secr). the clock polarity is set by cpol to select between act ive-high or active-low (the transfer format is unaf- fected). the clock phase is set by cpha. the master device an d the slave devices to communicate with must have the same clock phase and polarity. if multiple slave devices with differ ent transfer formats exis t on the same bus, the format can be changed to that of the slave device to which to transfer. 11.3.2 sei data and clock timing the programmable data and clock timing of sei allows connection to almost all synchronous serial periph- eral devices. refer to section ?" 11.5 sei transfer formats "?. table 11-2 clock phase and polarity cpha sei control register (secr 002ah) bit 2 cpol sei control register (secr 002ah) bit 3
page 117 TMP86F409NG 11.4 sei pin functions the TMP86F409NG have four input/output pins associat ed with sei transfer. th e functionality of each pin depends on the sei device?s mode (master or slave). the sclk pin, mosi pin and miso pin of all sei devices are connected with the same name pin to each other . 11.4.1 sclk pin the sclk pin functions as an output pin when sei is se t for master, or as an input pin when sei is set for slave. when sei is set for master, serial clock is output from the sclk pin to external devices. after the master starts transfer, eight serial cl ock pulses are output from the sclk pin only during transfer. when sei is set for slave, the sclk pin functions as an input pin. during data transfer between master and slave, device operation is synchronized by the serial clock output from the master. when the ss pin of the slave device is ?h?, data is not taken in regardless of whether the serial clock is avail- able. for both master and slave devices, data is shifted in and ou t at a rising or falling edge of the serial clock, and is sampled at the opposite edge where the data is stable . the active edge is determin ed by sei transfer proto- cols. note:noise in a slave device?s sclk input may cause the device to operate erratically. 11.4.2 miso/mosi pins the miso and mosi pins are used for serial data tr ansmission/reception. the stat us of each pin during mas- ter and slave are shown in the table below. also, the sclk, mosi, and miso pins can be set fo r open-drain by the each pin?s input/output control reg- ister (in case p0 port, input/output control register is p0outcr). the miso pin of a slave device b ecomes an output when the secr bit is set to 1 (sei operation enabled). to set the miso pin of an inactive slave device to a high-imped ance state, clear the secr bit to 0. 11.4.3 ss pin the ss pin function differently when the sei is the master and when it is a slave. when the sei is a slave, this pin is used to en able the sei transmission/r eception. when the slave?s ss pin is high, the slave device ignores the seri al clock from the master. nor does it receive data from the miso pin. when the slave?s ss pin is l, the sei operates as slave. table 11-3 miso/mosi pin status miso mosi master input output slave output input
page 118 11. serial expansion interface (sei) 11.5 sei transfer formats TMP86F409NG 11.5 sei transfer formats the transfer formats are set using cpha and cpol (secr). cpha allows transfer protocols to be selected between two. 11.5.1 cpha (secr regi ster bit 2) = 0 format figure 11-2 shows a transfer format where cpha = 0. figure 11-2 transfer format where cpha = 0 ? in master mode, transfer is initiated by writing ne w data to the sedr register. at this time, the new data changes state on the mosi pin a half clock period before the shift clock starts pulsing. use bos (secr) to select whether the data should be shifted out beginning with the msb or lsb. the sef flag (sesr) is set after the last shift cycle. ? in slave mode, writing data to the sedr register is inhibited when the ss pin is ?l?. a write during this period causes collision of writes, so that the wcol flag (sesr) is set. therefore, when writing data to th e sedr (sei data register) after the sef flag is set upon comple- tion of transfer, make sure the ss pin goes ?h? again before writing th e next data to the sedr register. note:in slave mode, be careful not to write data while the sef flag is set and the ss pin remains ?l?. 11.5.2 cpha = 1 format figure 11-3 shows a transfer format where cpha = 1. table 11-4 transfer format details where cpha = 0 sclk level when not communicating (idle) data shift data sampling cpol = 0 ?l? level falling edge of transfer clock rising edge of transfer clock cpol = 1 ?h? level rising edge of transfer clock falling edge of transfer clock sclk cycle sclk (cpol = 0) sclk (cpol = 1) mosi miso ss sef 1 2 3 4 5 6 7 8 internal shift clock secr
page 119 TMP86F409NG figure 11-3 transfer format where cpha = 1 ? in master mode, transfer is initiated by writing new data to the sedr register. the new data changes state on the mosi pin at the first edge of the shif t clock. use bos (secr) to select whether the data should be shifted out beginning with the msb or lsb. ? in slave mode, unlike in the case of cpha = 0 format, data can be written to the sedr (sei data reg- ister) regardless of whether the ss pin is ?l? or ?h?. in both master and slave modes, the sef flag (sesr) is set after the last shift cycle. writing data to the sedr register while data transf er is in progress causes collision of writes. there- fore, wait until the sef flag is set before writing new data to the sedr register. table 11-5 transfer format details where cpha = 1 sclk level when not communicating (idle) data shift data sampling cpol=0 ?l? level rising edge of transfer clock falling edge of transfer clock cpol=1 ?h? level falling edge of transfer clock rising edge of transfer clock sclk cycle sclk (cpol = 0) sclk (cpol = 1) mosi miso ss sef 1 2 3 4 5 6 7 8 internal shift clock secr
page 120 11. serial expansion interface (sei) 11.6 functional description TMP86F409NG 11.6 functional description figure 11-4 shows how the sei master and slave are connected. when the master device sends data from its mosi pin to a slave device?s mosi pin, the slave device returns data from its miso pin to the master device?s miso pin. this means that data are exchanged between master and slave via full-duplex communication, with data output and input operations synchronized by the same clock signal. after end of transfer, the transmit byte in 8 bit shif t register is replaced with the receive byte. figure 11-4 master and slave connection in sei 8-bit shift register sei clock ss 8-bit shift register mosi master slave miso sclk mosi miso sclk 5 v 0v ss
page 121 TMP86F409NG 11.7 interrupt generation the sei for the TMP86F409NG uses ints ei1. when the sesr changes st ate from ?0? to ?1?, respective interrupts is generated. 11.8 sei system errors the sei has the facility to det ect following two system errors. ? write collision error: when the sedr register is acce ssed for write during transfer. ? overflow error: when the new data byte is shift in before the previous data byte is read in slave mode. 11.8.1 write collision error collision of writes occurs when an attempt is made to write to the sedr register while transfer is in progress. because the sedr register is not configured as dual-buffers when sending data, a write to the sedr register directly results in writing to the sei shift regi ster. therefore, writing to th e sedr register while trans- fer is in progress causes a write collision error. in no case is data transfer stopped in the middle, so that the write data which caused a write collision error will not be written to the shift regist er. because slaves cannot control the timing at which the master starts a transfer, collision of writes norma lly occurs on the slave side. write collision errors do no t normally occur on the master side because the master has the right to perform a transfer at any time, but in view of sei logic both the master and slaves have the facility to detect write colli- sion errors. a write collision error tends to occur on the slave side when the master sh ifts out data at a speed faster than that at which the slave processes the transferred data. more specifically, a write col lision error occurs in cases where the slave transfers a ne w value to the sedr register when the master already st arted a shift cycle for the next byte. 11.8.2 overflow error the transfer bit rate on the sei bus is determined by the master. a high bit rate causes a problem that a slave cannot keep abreast with transf er from the master, because the master is shifting out data faster than can be pro- cessed by the slave. the sei module uses the sovf flag (ses r) to detect that data has overflowed. the sovf flag is set in the following cases: ? when the sei module is set for slave ? when the old data byte remains to be read while a new data byte has been received when the sovf flag is set, the sedr regi ster is overwritten with a new data byte. note:please carefully examine the communication proc essing routine and communication rate when designing your application system. table 11-6 sei interrupt sei interrupt channel 1 (intsei1) interrupt generated for sef
page 122 11. serial expansion interface (sei) 11.9 bus driver protection TMP86F409NG 11.9 bus driver protection ? one method to protect the device against latch-up due to collision of the bus drivers is the use of an open- drain option. this means changing the sei pins? cmos outputs to the open-drain type, which is accom- plished by setting the sclk, mosi, a nd miso pins for open-drain indi vidually by using the each port input/output control register. in this case, these pins mu st be provided with pull-up resistors external to the chip. ? when using the sei pins as cmos outputs, we recommend connecting them to the bus via resistors in order to protect the device against collision of drivers. however, be sure to se lect the appropriate resistance value which will not affect actual device operation (example: 1 ? to several k ? ).
page 123 TMP86F409NG 12. 10-bit ad converter (adc) the TMP86F409NG have a 10-bit successive approximation type ad converter. 12.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 12-1. it consists of control register adccr1 and adccr2 , converted value register adcdr1 and adcdr2, a da converter, a sample-hold circuit, a compar ator, and a successive comparison circuit. note: before using ad converter, set appropriate value to i/o port register conbining a analog input port. for details, see the sec- tion on "i/o ports". figure 12-1 10-bit ad converter 2 4 10 8 ainds adrs r/2 r/2 r ack amd irefon ad conversion result register 1, 2 ad converter control register 1, 2 adbf eocf intadc sain n successive approximate circuit adccr2 adcdr1 adcdr2 adccr1  sample hold circuit a s en shift clock da converter analog input multiplexer y reference voltage analog comparator 2 3 control circuit vss vdd vdd ain0 ain5
page 124 12. 10-bit ad converter (adc) 12.2 register configuration TMP86F409NG 12.2 register configuration the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels and operatio n mode (software start or repeat) in which to per- form ad conversion and controls the ad converter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time and co ntrols the connection of the da converter (ladder resistor network). 3. ad converted value register 1 (adcdr1) this register used to store the digital value fter being converted by the ad converter. 4. ad converted value register 2 (adcdr2) this register monitors the oper ating status of the ad converter. note 1: select analog input channel during ad converter stops (adcdr2 = "0"). note 2: when the analog input channel is all use dis abling, the adccr1 should be set to "1". note 3: during conversion, do not perform port output instruction to maintain a precision for all of the pins because analog inp ut port use as general input port. and for port near to anal og input, do not input intense signaling of change. note 4: the adccr1 is automatically cleared to "0" after starting conversion. note 5: do not set adccr1 newly again during ad conv ersion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop or slow/sleep mode are started, ad conver ter control register1 (adccr1) is all initialized and no data can be written in this register. therfore, to use ad converter again, set the adccr1 newly after returning to normal1 or normal2 mode. ad converter control register 1 adccr1 (000eh) 76543210 adrs amd ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: - ad conversion start r/w amd ad operating mode 00: 01: 10: 11: ad operation disable software start mode reserved repeat mode ainds analog input control 0: 1: analog input enable analog input disable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
page 125 TMP86F409NG note 1: always set bit0 in adccr2 to "0" and set bit4 in adccr2 to "1". note 2: when a read instruction for adccr2, bi t6 to 7 in adccr2 read in as undefined data. note 3: after stop or slow/sleep mode are started, ad conver ter control register2 (adccr2) is all initialized and no data can be written in this register. therfore, to use ad converter again, set the adccr2 newly after returning to normal1 or normal2 mode. note 1: setting for " ?
page 126 12. 10-bit ad converter (adc) 12.2 register configuration TMP86F409NG note 1: the adcdr2 is cleared to "0" when reading the a dcdr1. therfore, the ad conversion result should be read to adcdr2 more first than adcdr1. note 2: the adcdr2 is set to "1" when ad conversion star ts, and cleared to "0" when ad conversion finished. it also is cleared upon entering stop mode or slow mode . note 3: if a read instruction is executed for a dcdr2, read data of bit3 to bit0 are unstable. eocf ad conversion end flag 0: 1: before or during conversion conversion completed read only adbf ad conversion busy flag 0: 1: during stop of ad conversion during ad conversion
page 127 TMP86F409NG 12.3 function 12.3.1 software start mode after setting adccr1 to ?01? (software start mode), set adccr1 to ?1?. ad conver- sion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. adrs is automatically cleared afte r ad conversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adrs newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signa l (intadc) is generated (e.g., interrupt handling rou- tine). figure 12-2 software start mode 12.3.2 repeat mode ad conversion of the voltage at the analog input pin specified by adccr1 is performed repeatedly. in this mode, ad conversion is started by setti ng adccr1 to ?1? after setting adccr1 to ?11? (repeat mode). after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1, adcdr2) and at the same time adcdr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. in repeat mode, each time one ad conversion is complete d, the next ad conversion is started. to stop ad conversion, set adccr1 to ?00? (disable mode) by writing 0s. the ad convert operation is stopped immediately. the converted valu e at this time is not stored in the ad converted value register. adcdr1 status eocf cleared by reading conversion result conversion result read adcdr2 intadc interrupt request adcdr2 adccr1 1st conversion result 2nd conversion result indeterminate ad conversion start ad conversion start a dcdr1 a dcdr2 conversion result read conversion result read conversion result read
page 128 12. 10-bit ad converter (adc) 12.3 function TMP86F409NG figure 12-3 repeat mode 12.3.3 regi ster setting 1. set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). ? specify amd for the ad converter control operation mode (software or repeat mode). 2. set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to figure 12-1 and ad converter control register 2. ? choose irefon for da converter control. 3. after setting up (1) and (2) above, set ad conversion start (adrs) of ad converter control register 1 (adccr1) to ?1?. if software start mode has been selected, ad conversi on starts immediately. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdr1) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdr2) is set to ?1?, upon wh ich time ad conversion interrupt intadc is gener- ated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. a dcdr1,adcdr2 eocf cleared by reading conversion result conversion result read a dcdr2 intadc interrupt request conversion operation a dccr1 indeterminate ad conversion start adccr1 ?11? ?00? 1st conversion result ad convert operation suspended. conversion result is not stored. 2nd conversion result 3rd conversion result a dcdr1 a dcdr2 2nd conversion result 3rd conversion result 1st conversion result conversion result read conversion result read conversion result read conversion result read conversion result read
page 129 TMP86F409NG 12.4 stop/slow modes during ad conversion when standby mode (stop or slow mode) is entered fo rcibly during ad conversi on, the ad convert operation is suspended and the ad converter is in itialized (adccr1 and adccr2 are initia lized to initial value). also, the conversion result is indeterminate. (conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode (sto p or slow mode).) when restored from standby mode (stop or slow mode), ad conversion is not automatically restarted, so it is necessa ry to restart ad conversion. note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage. example :after selecting the conversion time 19.5 s at 16 mhz and the analog input channel ain3 pin, perform ad con- version once. after checking eocf, read the converted value, store the lower 2 bits in address 0009eh nd store the upper 8 bits in address 0009fh in ram. the operation mode is software start mode. : (port setting) : ;set port register approrriately before setting ad converter registers. : : (refer to section i/o port in details) ld (adccr1) , 00100011b ; select ain3 ld (adccr2) , 11011000b ;select conversion time(312/fc) and operation mode set (adccr1) . 7 ; adrs = 1(ad conversion start) sloop : test (adcdr2) . 5 ; eocf= 1 ? jrs t, sloop ld a , (adcdr2) ; read result data ld (9eh) , a ld a , (adcdr1) ; read result data ld (9fh), a
page 130 12. 10-bit ad converter (adc) 12.5 analog input voltage and ad conversion result TMP86F409NG 12.5 analog input voltage and ad conversion result the analog input voltage is corresponded to the 10-bit dig ital value converted by the ad as shown in figure 12-4. figure 12-4 analog i nput voltage and ad c onversion result (typ.) 1 0 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 analog input voltage 1024 ad conversion result vdd vss
page 131 TMP86F409NG 12.6 precautions about ad converter 12.6.1 analog input pin voltage range make sure the analog input pins (ain0 to ain5) are us ed at voltages within vdd to vss. if any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. 12.6.2 analog input shared pins the analog input pins (ain0 to ain5) are shared w ith input/output ports. when using any of the analog inputs to execute ad conversion, do not execute input/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input sh ared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 12.6.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 12-5. the higher the output impedance of the analog input source, more easily they are susceptible to no ise. therefore, make sure the out- put impedance of the signal source in your design is 5 k ? or less. toshiba also recommends attaching a capac- itor external to the chip. figure 12-5 analog i nput equivalent circuit and exam ple of input pin processing da converter aini analog comparator internal resistance permissible signal source impedance internal capacitance 5 k ? ?
page 132 12. 10-bit ad converter (adc) 12.6 precautions about ad converter TMP86F409NG
page 133 TMP86F409NG 13. key-on wakeup (kwu) TMP86F409NG have four pins p34 to p37, in addition to the p20 ( int5 / stop ) pin, that can be used to exit stop mode. when using these p34 to p37 pin?s input to exit stop mode, pay attention to the logic of p20 pin. in details, refer to the following section" 13.2 control ". 13.1 configuration figure 13-1 key-on wakeup circuit figure 13-2 example of st op mode release operation int5 p20 (int5/stop) p34 (ain2/stop2) p35 (ain3/stop3) stop mode release signal (1: release) stop mode control qd s stop2(stopcr) stop signal qd s stop3(stopcr) stop signal p36 (ain4/stop4) qd s stop4(stopcr) stop signal p37 (ain5/stop5) qd s stop5(stopcr) stop signal stop mode release operation(p34 to 37) example of stop mode release operation "l" "h" "l" rising or falling edge detect stop wake-up* operation the time required for wakeup from releasing stop mode includes the warming-up time. for details, refer to section "control of operation modes". p3i *
page 134 13. key-on wakeup (kwu) 13.2 control TMP86F409NG 13.2 control the p34 to p37 (stop2 to stop5) pins can individuall y be disabled/enabled using key-on wakeup control reg- ister (stopcr). before these pins can be used to place th e device out of stop mode, th ey must be set for input using the p3 port input/out put register (p3cr), p3port output latc h (p3dr), ad contro l register (adccr1). stop mode can be entered by setting up the system contro l register (syscr1), and ca n be released by detecting the active edge (rising or falling edge) on any stop2 to st op5 pins which are available for stop mode release. note: when using key-on wakeup function, select level mode ( set syscr1 to "1" ) for selection of stop mode release method. although p20 pin is shared with int5 and stop pin input, use mainly stop pin to release stop mode. this is because key-on wakeup fu nction is comprised of stop pin and stop2 to stop5 pins as shown in the configuration diagram. note 1: when stop mode release by an edge on stop pi n, follow one of the two methods described below. (1) disable all of stop2 to 5 pin inputs. (2) fix stop2 to 5 pin inputs high or low level. note 2: when using key-on wakeup (stop2 to 5 pins) to exit stop mode, make sure stop pin is held low and stop2 to 5 pin inputs are held high or low level, because stop mode release signal is created by oring the stop pin input and the stop2 to 5 pin input together. note: assertion of the stop mode release si gnal is not recognized within three inst ruction cycles after executing the stop instruction. key-on wakeup stop mode control register stopcr76543210 (0031h) stop5 stop4 stop3 stop2 (initial value : 0000 ****) stop2 stop mode release by p34 (stop2) 0: disable write only 1: enable stop3 stop mode release by p35 (stop3) 0: disable 1: enable stop4 stop mode release by p36 (stop4) 0: disable 1: enable stop5 stop mode release by p37 (stop5) 0: disable 1: enable the device is released from stop mode in the following condition. p20( stop )p3x stop mode release using p3x (stop2 to 5) level detection mode: low edge detection mode: disable edge detection rising or falling edge stop mode release using p20 ( stop ) level detection mode: high edge detection mode: rising edge stopcr: inhibited
page 135 TMP86F409NG 14. flash memory TMP86F409NG has 4096byte flash memory (address: f000h to ffffh). the write and erase operations to the flash memory are controlled in th e following three types of mode. - mcu mode the flash memory is accessed by the cpu control in the mcu mode. this mode is used for software bug correction and firmware change after shipment of the device since the write operation to the flash memory is available by retaining the application behavior. - serial prom mode the flash memory is accessed by the cpu control in th e serial prom mode. use of the serial interface (uart) enables the flash memory to be controlled by the small number of pins. TMP86F409NG in the serial prom mode supports on-board programming wh ich enables users to prog ram flash memory after the microcontroller is mounted on a user board. - parallel prom mode the parallel prom mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provided by the third party. high-speed access to th e flash memory is available by control- ling address and data signals directly. for the suppor t of the program writer, please ask toshiba sales rep- resentative. in the mcu and serial prom modes, the flash memory c ontrol register (flscr) is used for flash memory con- trol. this chapter describes how to acce ss the flash memory using the flash memo ry control register (flscr) in the mcu and serial prom modes.
page 136 14. flash memory 14.1 flash memory control TMP86F409NG 14.1 flash memory control the flash memory is controlled via the flash memory control register (flscr) and flash memory stanby control resister (flsstb). note 1: the command sequence of the flash me mory can be executed only when flsmd=" 0011b". in other cases, any attempts to execute the command sequence are ineffective. note 2: flsmd must be set to either "1100b" or "0011b". note 3: bits 3 through 0 in flscr are always read as don?t care. note 1: when fstb is set to 1, do not execute the read/write in struction to the flash memory bec ause there is a possibility that the expected data is not read or the program is not operated correctl y. if executing the read/write instruction, fstb is initial- ized to 0 automatically. note 2: if an interrupt is issued when fstb is set to 1, fstb is initialized to 0 automatically and then the vector area of the flash memory is read. note 3: if the idle0/1/2, sleep0/1/2 or stop mode is activated when fstb is set to 1, fstb is initialized to 0 automatically. in the idle0/1/2, sleep0/1/2 or stop mode, the standby function operates regardless of fstb setting. 14.1.1 flash memory command sequenc e execution control (flscr) the flash memory can be protected fr om inadvertent write due to program error or microcontroller misoper- ation. this write protection feature is realized by disabling flash memo ry command sequence execution via the flash memory control register (write protect). to enable command sequence execution, set flscr to ?0011b?. to disable comman d sequence execution, set flscr to ?1100b?. after reset, flscr is initialized to ?1100b? to disable command sequence execution. normally, flscr should be set to ?1100b? except when the flash memory needs to be written or erased. 14.1.2 flash memory stan dby control (flsstb) low power consumption is enabled by cutting off the steady-state current of the flash memory. in the idle0/1/2, sleep0/1/2 or stop mode, th e steady-state current of the flas h memory is cut off automatically. when the program is executed in the ram area (with out accessing the flash me mory) in the normal 1/2 or slow1/2 mode, the current can be cut off by the contro l of the register. to cut off the steady-state current of the flash memory, set flsstb to ?1? by the c ontrol program in the ram area. the procedures for controlling the flsstb regi ster are explained below. (steps1 and 2 are controlled by the program in the flash memory, and steps 3 through 8 are controlled by the write control program ex ecuted in the ram area.) flash memory control register flscr76543210 (0fffh) flsmd (initial value : 1100 ****) flsmd flash memory command sequence exe- cution control 1100: disable command sequence execution 0011: enable command sequence execution others: reserved r/w flash memory standby control register flsstb76543210 (0fe9h) fstb (initial value : **** ***0) fstb flash memory standby control 0: disable the standby function. 1: enable the standby function. write only
page 137 TMP86F409NG 1. transfer the control program of th e flsstb register to the ram area. 2. jump to the ram area. 3. disable (di) the interrupt mast er enable flag (imf = ?0?). 4. set flsstb to ?1?. 5. execute the user program. 6. repeat step 5 until the return requ est to the flash memory is detected. 7. set flsstb to ?0?. 8. jump to the flash memory area. note 1: the standby function is not operated by setting fl sstb with the program in the flash memory. you must set flsstb by the program in the ram area. note 2: to use the standby function by setting flsstb to ?1? with the program in the ram area, flsstb must be set to ?0? by the program in the ram area before returning the program control to the flash memory. if the program control is returned to the flash memory with flsstb set to ?1?, the program may misoperate and run out of control.
page 138 14. flash memory 14.2 command sequence TMP86F409NG 14.2 command sequence the command sequence in the mcu and the serial prom modes consists of six commands (jedec compatible), as shown in table 14-1. addresses specified in the command sequence are recogni zed with the lower 12 bits (excluding ba, sa, and ff7fh used for read protection). the upper 4 bits are used to specify the flash memory area, note 1: set the address and data to be written. note 2: the area to be erased is specified with the upper 4 bits of the address. 14.2.1 byte program this command writes the fl ash memory for each byte unit. the addresse s and data to be written are specified in the 4th bus write cycle. each byte can be programmed in a maximum of 40 s. the next command sequence cannot be executed until the write operation is completed. to check the completion of the write operation, per- form read operations repeat edly until the same data is read twice fr om the same address in the flash memory. during the write operation, any consecutive attempts to r ead from the same address is reversed bit 6 of the data (toggling between 0 and 1). note:to rewrite data to flash memory addresses at which dat a (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data. 14.2.2 sector erase (4-kbyte erase) this command erases the flash memory in units of 4 k bytes. the flash memory area to be erased is specified by the upper 4 bits of the 6th bus write cycle address. for example, to erase 4 kbytes from f000h to ffffh, specify one of the addresses in f000 h-ffffh as the 6th bus wr ite cycle. the sector erase command is effec- tive only in the mcu and serial prom modes, and it cannot be used in the parallel prom mode. a maximum of 30 ms is required to erase 4 kbytes. the next command sequence cannot be executed until the erase operation is completed. to check the completion of the erase operation, perf orm read operations repeat- edly for data polling until the same data is read twice from the same address in the flash memory. during the erase operation, any consecutive attempts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). table 14-1 command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle address data address data address data address data address data address data 1 byte program 555h aah aaah 55h 555h a0h ba (note 1) data (note 1) ---- 2 sector erase (4-kbyte erase) 555h aah aaah 55h 555h 80h 555h aah aaah 55h sa (note 2) 30h 3 chip erase (all erase) 555h aah aaah 55h 555h 80h 555h aah aaah 55h 555h 10h 4product id entry555haahaaah55h555h90h------ 5 product id exitxxhf0h---------- product id exit555haahaaah55h555hf0h------ 6read protect555haahaaah55h555ha5hff7fh00h----
page 139 TMP86F409NG 14.2.3 chip erase (all erase) this command erases the entire flash memory in appr oximately 30 ms. the next command sequence cannot be executed until the erase operation is completed. to check the completio n of the erase operation, perform read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory. during the erase operation, any consecutive attemp ts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). after the chip is erased, all bytes contain ffh. 14.2.4 product id entry this command activates the product id mode. in the product id mode, the vendor id, the flash id, and the read protection status can be read from the flash memory. note: the value at address f002h (flash size) depends on the size of flash memory incorporated in each product. for example, if the product has 60-kbyte flash memory, "0eh" is read from address f002h. 14.2.5 product id exit this command is used to exit the product id mode. 14.2.6 read protect this command enables the r ead protection setting in the flash memory . when the read protection is enabled, the flash memory cannot be read in the parallel prom mode. in the seri al prom mode, the flash write and ram loader commands cannot be executed. to disable the read protection setting, it is necessary to execute the chip eras e command sequence. whether or not the read protection is enabled can be checked by reading ff7fh in the product id mode. for details, see table 14-2. it takes a maximum of 40 s to set read protection in the flash memory. the next command sequence cannot be executed until this operation is completed. to check the completion of the read protect operation, perform read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory. during the read protect operation, any attempts to read from the same address is reversed bit 6 of the data (toggling between 0 and 1). table 14-2 values to be read in the product id mode address meaning read value f000h vendor id 98h f001h flash macro id 41h f002h flash size 0eh: 60 kbytes 0bh: 48 kbytes 07h: 32 kbytes 05h: 24 kbytes 03h: 16 kbytes 01h: 8 kbytes 00h: 4 kbytes ff7fh read protection status ffh: read protection disabled other than ffh: read protection enabled
page 140 14. flash memory 14.3 toggle bit (d6) TMP86F409NG 14.3 toggle bit (d6) after the byte program, chip erase, and read protect command sequence is executed, any consecutive attempts to read from the same address is reversed bit 6 (d6) of the data (toggling between 0 and 1) until the operation is com- pleted. therefore, this toggle bit provides a software mechanism to check the completion of each operation. usually perform read operations repeatedly for data polling until th e same data is read twice from the same address in the flash memory. after the byte program, chip erase, or read protect command sequence is executed, the initial read of the toggle bit always produces a "1".
page 141 TMP86F409NG 14.4 access to the flash memory area when the write, erase and read protect ions are set in the flash memory, read and fetch operations cannot be per- formed in the entire flash memory area. therefore, to perform these operations in the entire flash memory area, access to the flash memory area by the control program in the bootrom or ram area. (the flash memory pro- gram cannot write to the flash memory.) the serial prom or mcu mode is used to run the control program in the bootrom or ram area. note 1: the flash memory can be written or read for each by te unit. erase operations can be performed either in the entire area or in units of 4 kbytes, whereas read operations can be performed by an one transfer instruction. however, the command sequence method is adopted for write and erase operations, requiring several-byte transfer instruc- tions for each operation. note 2: to rewrite data to flash memory addresses at which data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data. 14.4.1 flash memory contro l in the serial prom mode the serial prom mode is used to access to the fl ash memory by the contro l program provided in the bootrom area. since almost of all op erations relating to access to the flash memory can be controlled sim- ply by the communication data of th e serial interface (uart), these functio ns are transparent to the user. for the details of the serial prom mode, see ?serial prom mode.? to access to the flash memory by using peripheral func tions in the serial prom mode, run the ram loader command to execute the control prog ram in the ram area. the procedures to execute the control program in the ram area is shown in " 14.4.1.1 how to write to the flash memory by executing the control program in the ram area (in the ram loader mode within the serial prom mode) ". 14.4.1.1 how to write to the flash memory by executing the control program in the ram area (in the ram loader mode within the serial prom mode) (steps 1 and 2 are controlled by the bootrom, and steps 3 through 9 are controlled by the control program executed in the ram area.) 1. transfer the write control program to the ram area in the ram loader mode. 2. jump to the ram area. 3. disable (di) the interrup t master enable flag (imf "0"). 4. set flscr to "0011b" (to enable command sequence execution). 5. execute the erase command sequence. 6. read the same flash memory address twice. (repeat step 6 until the same data is re ad by two consecutive reads operations.) 7. execute the write command sequence. 8. read the same flash memory address twice. (repeat step 8 until the same data is read by two consecutive reads operations.) 9. set flscr to "1100b" (to disable command sequence execution). note 1: before writing to the flash memory in the ram area, disable interrupts by setting the interrupt master enable flag (imf) to "0". usually disable interrupts by executing the di instruction at the head of the write control program in the ram area. note 2: since the watchdog timer is disabled by the boot rom in the ram loader mode, it is not required to disable the watchdog timer by the ram loader program.
page 142 14. flash memory 14.4 access to the flash memory area TMP86F409NG example :after chip erasure, the program in the ram area writ es data 3fh to address f000h. di : disable interrupts (imf
page 143 TMP86F409NG 14.4.2 flash memory c ontrol in the mcu mode in the mcu mode, write operations are performed by executing the control program in the ram area. before execution of the control pr ogram, copy the control program into the ram area or obtain it from the external using the communication pin. the procedures to execute the cont rol program in the ram area in the mcu mode are described below. 14.4.2.1 how to write to the flash memory by executing a user write control program in the ram area (in the mcu mode) (steps 1 and 2 are controlled by the program in the flash memory, and steps 3 through 11 are controlled by the control program in the ram area.) 1. transfer the write contro l program to the ram area. 2. jump to the ram area. 3. disable (di) the interrup t master enable flag (imf "0"). 4. disable the watchdog timer, if it is used. 5. set flscr to "0011b" (to enable command sequence execution). 6. execute the erase command sequence. 7. read the same flash memory address twice. (repeat step 7 until the same data is read by two consecutive read operations.) 8. execute the write command sequence. 9. read the same flash memory address twice. (repeat step 9 until the same data is read by two consecutive read operations.) 10. set flscr to "1100b" (to disable command sequence execution). 11. jump to the flash memory area. note 1: before writing to the flash memory in the ram area, disable interrupts by setting the interrupt master enable flag (imf) to "0". usually disable interrupts by executing the di instruction at the head of the write control program in the ram area. note 2: when writing to the flash memory, do not in tentionally use non-maskable interrupts (the watchdog timer must be disabled if it is used). if a non-mask able interrupt occurs while the flash memory is being written, unexpected data is read from the flash memory (interrupt vector), resulting in malfunc- tion of the microcontroller.
page 144 14. flash memory 14.4 access to the flash memory area TMP86F409NG example :after sector eras ure (e000h-efffh), the program in the ram area writes data 3fh to address e000h. di : disable interrupts (imf example :this write control program reads data from address f000h and stores it to 98h in the ram area. ld a,(0f000h) : read data from address f000h. ld (98h),a : store data to address 98h.
page 145 TMP86F409NG 15. serial prom mode 15.1 outline the TMP86F409NG has a 2048 byte bootrom (mask rom) for programming to flash memory. the bootrom is available in the serial prom mode, and controlled by test, boot and reset pins. communica- tion is performed via uart. the serial prom mode ha s seven types of operating mode: flash memory writing, ram loader, flash memory sum output, product id code output, flash memory status output, flash memory eras- ing and flash memory read protection setting. memory addr ess mapping in the serial pr om mode differs from that in the mcu mode. figure 15-1 shows memory address mapping in the serial prom mode. note: though included in above operating range, some of high fr equencies are not supported in the serial prom mode. for details, refer to ?table 15-5?. 15.2 memory mapping the figure 15-1 shows memory mapping in the serial prom mode and mcu mode. in the serial prom mode, the bootrom (mask rom) is mapped in addresses from 7800h to 7fffh. figure 15-1 memory address maps table 15-1 operating range in the serial prom mode parameter min max unit power supply 4.5 5.5 v high frequency (note) 2 16 mhz 003fh 0000h 64 bytes 2048 bytes 0040h 7800h 7fffh f000h ffffh ffffh sfr ram dbr sfr ram dbr bootrom flash memory serial prom mode mcu mode 4096 bytes 003fh 0000h 64 bytes 0040h flash memory f000h 4096 bytes 0fffh 0fffh 512 bytes 128 bytes 128 bytes 023fh 0f80h 0f80h 512 bytes 023fh
page 146 15. serial prom mode 15.3 serial prom mode setting TMP86F409NG 15.3 serial prom mode setting 15.3.1 serial prom mode control pins to execute on-board programming, act ivate the serial prom mode. table 15-2 shows pin setting to activate the serial prom mode. note: the boot pin is shared with the uart communication pin (rxd 0 pin) in the serial prom mode. this pin is used as uart communication pin after activating serial prom mode 15.3.2 pin function in the serial prom mode, txd0 (p03) and rxd0 (p02) are used as a serial interface pin. note 1: during on-board programming with other parts mounted on a user board, be careful no to affect these communication control pins. note 2: operating range of high frequency in serial prom mode is 2 mhz to 16 mhz. table 15-2 serial prom mode setting pin setting test pin high boot/rxd0 pin high reset pin table 15-3 pin function in the serial prom mode pin name (serial prom mode) input/ output function pin name (mcu mode) txd0 output serial data output (note 1) p03 boot/rxd0 input/input serial prom mode control/serial data input p02 reset input serial prom mode control reset test input fixed to high test vdd power supply 4.5 to 5.5 v vss power supply 0 v i/o ports except p03, p02 i/o these ports are in the high-impedance state in the serial prom mode. the input level is fixed to the port inputs with a hardware feature to prevent overlap current. (the port inputs are invalid.) to make the port inputs valid, set the pin of the spcr register to ?1? by the ram loader control pro- gram. xin input self-oscillate with an oscillator. (note 2) xout output
page 147 TMP86F409NG figure 15-2 serial prom mode pin setting note 1: for connection of other pins, refer to " t able 15-3 pin function in the serial prom mode ". 15.3.3 example connection for on-board writing figure 15-3 shows an example connection to perform on-board wring. figure 15-3 example conn ection for on-board writing note 1: when other parts on the application board effect th e uart communication in the serial prom mode, iso- late these pins by a jumper or switch. note 2: when the reset control circuit on the application board effect s activation of the serial prom mode, isolate the pin by a jumper or switch. note 3: for connection of other pins, refer to " t able 15-3 pin function in the serial prom mode ". vdd(4.5 v to 5.5 v) serial prom mode mcu mode vdd test reset external control pull-up xin xout vss gnd boot / rxd0 (p02) txd0 (p03) TMP86F409NG vdd(4.5 v to 5.5 v) serial prom mode mcu mode vdd test reset pc control pull-up level converter xin xout vss gnd external control board application board rc power-on reset circuit reset control other parts (note 1) (note 2) boot / rxd0 (p02) txd0 (p03)
page 148 15. serial prom mode 15.3 serial prom mode setting TMP86F409NG 15.3.4 activating t he serial prom mode the following is a procedure to ac tivate the serial prom mode. " figure 15-4 serial prom mode timing " shows a serial prom mode timing. 1. supply power to the vdd pin. 2. set the reset pin to low. 3. set the test pin and boot/rxd0 pins to high. 4. wait until the power supply and clock oscillation stabilize. 5. set the reset pin to high. 6. input the matching data (5ah) to the boot/rxd0 pin after setup sequence. for details of the setup timing, refer to " 15.16 uart timing ". figure 15-4 serial prom mode timing vdd test(input) reset(input) program setup time for serial prom mode (rxsup) high level setting matching data don't care reset mode serial prom mode input boot/rxd0 (input)
page 149 TMP86F409NG 15.4 interface specifications for uart the following shows the uart communication format used in the serial prom mode. to perform on-board programming, the communication format of the write controller must also be set in the same manner. the default baud rate is 9600 bps regardless of operating frequency of the microcontroller. the baud rate can be modified by transmitting the baud rate modification data shown in table 1-4 to TMP86F409NG. the table 15-5 shows an operating frequency and baud rate. the frequencies which are not described in table 15-5 can not be used. - baud rate (default): 9600 bps - data length: 8 bits - parity addition: none - stop bit: 1 bit table 15-4 baud rate modification data baud rate modification data 04h 05h 06h 07h 0ah 18h 28h baud rate (bps) 76800 62500 57600 38400 31250 19200 9600
page 150 15. serial prom mode 15.4 interface specifications for uart TMP86F409NG note 1: ?ref. frequency? and ?rating? show frequencies availabl e in the serial prom mode. though the frequency is supported in the serial prom mode, the serial prom mode may not be activated correctly due to the frequency difference in the external controller (such as pers onal computer) and oscillator, and load capacitance of communication pins. note 2: it is recommended that the total frequency difference is within
page 151 TMP86F409NG 15.5 operation command the eight commands shown in table 15-6 are used in the serial prom mode. after reset release, the TMP86F409NG waits for the matching data (5ah). 15.6 operation mode the serial prom mode has seven types of modes, that are (1) flash memory erasin g, (2) flash memory writing, (3) ram loader, (4) flash memory sum output, (5) product id code output, (6) flash memory status output and (7) flash memory read protection setting modes. description of each mode is shown below. 1. flash memory erasing mode the flash memory is erased by the chip erase (erasing an entire flash area) or sector erase (erasing sectors in 4-kbyte units). the erased area is filled with ffh. when the read protection is enabled, the sector erase in the flash erasing mode can not be performed. to disabl e the read protection, perfor m the chip erase. before erasing the flash memory, tmp86f40 9ng checks the passwords except a blank product. if the password is not matched, the flash memory erasing mode is not activated. 2. flash memory writing mode data is written to the specified flas h memory address for each byte unit. the external controller must trans- mit the write data in the intel hex format (binary). if no error is encountered till the end record, TMP86F409NG calculates the checksum for the entire flash memory area (f000h to ffffh), and returns the obtained result to the external controller. when the read protection is enabled, the flash memory writing mode is not activated. in this case, perform the chip erase command beforehand in the flash memory eras- ing mode. before activating the flash memory wr iting mode, TMP86F409NG checks the password except a blank product. if the password is not matched, flash memory writing mode is not activated. 3. ram loader mode the ram loader transfers the data in intel hex format sent from the external controller to the internal ram. when the transfer is completed normally, the ram loader calculates the checksum. after transmit- ting the results, the ram loader jump s to the ram address specified with the first data record in order to execute the user program. when the read protection is enabled, the ram loader mode is not activated. in this case, perform the chip erase beforehand in the fl ash memory erasing mode. before activating the ram loader mode, TMP86F409NG ch ecks the password except a blank product. if the password is not matched, flash ram loader mode is not activated. 4. flash memory sum output mode the checksum is calculated for the entire flash memory area (f000h to ffffh), and the result is returned to the external controller. since the bootrom does not support the oper ation command to read the flash memory, use this checksum to identify programs when managing revisions of application programs. 5. product id code output the code used to identify the product is output. the code to be output consists of 13-byte data, which includes the information indicating th e area of the rom incorporated in the product. the external control- ler reads this code, and recognizes the product to write. (in the case of TMP86F409NG, the addresses from f000h to ffffh become the rom area.) table 15-6 operation command in the serial prom mode command data operating mode description 5ah setup matching data. execute this command after releasing the reset. f0h flash memory erasing erases the flas h memory area (address f000h to ffffh). 30h flash memory writing writes to the flash memory area (address f000h to ffffh). 60h ram loader writes to the specified ram area (address 0050h to 023fh). 90h flash memory sum output outputs the 2-byte checksum upper byte and lower byte in this order for the entire area of the flash memory (address f000h to ffffh). c0h product id code output outputs the product id code (13-byte data). c3h flash memory status output outputs the status code (7-byte data) such as the read protection condition. fah flash memory read protection setting enables the read protection.
page 152 15. serial prom mode 15.6 operation mode TMP86F409NG 6. flash memory status output mode the status of the area from ffe0h to ffffh, and the read protection co ndition are output as 7-byte code. the external controller reads this code to recognize the flash memory status. 7. flash memory read protection setting mode this mode disables reading the flash memory data in parallel prom mode. in the serial prom mode, the flash memory writing and ram loader modes are disabled. to disable th e flash memory read protection, perform the chip erase in th e flash memory erasing mode.
page 153 TMP86F409NG 15.6.1 flash memory erasi ng mode (operati ng command: f0h) table 15-7 shows the flash memory erasing mode. note 1: ?xxh description of the flash memory erasing mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. table 15-7 flash memory erasing mode transfer byte transfer data from the external controller to TMP86F409NG baud rate transfer data from TMP86F409NG to the external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: no data transmitted 3rd byte 4th byte baud rate change data (table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h
page 154 15. serial prom mode 15.6 operation mode TMP86F409NG 2. the 5th byte of the received data contains th e command data in the flash memory erasing mode (f0h). 3. when the 5th byte of the receive d data contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, f0h). if the 5th byte of the received data does not contai n the operation command data, the device enters the halt condition after sending 3 bytes of the operation command error code (63h). 4. the 7th thorough m'th bytes of the transmitted and received data contai n the same data as in the flash memory writing mode. in the case of a blank produc t, do not transmit a password string. (do not transmit a dummy password string.) 5. the n?th - 2 byte contains the erasure area specification data. the upper 4 bits and lower 4 bits specify the start address and end address of the erasure area, respectively. for the detailed description, see ?1.13 specifying the erasure area?. 6. the n?th - 1 byte and n?th byte contain the upper and lower bytes of the checksum, respectively. for how to calculate the checksum, refer to ?1.8 checksum (sum)?. checksum is calculated unless a receiving error or intel hex format error occurs. after sending the e nd record, the external controller judges whether the transmission is completed corr ectly by receiving the checksum sent by the device. 7. after sending the checksum, the device waits for the next operation command data.
page 155 TMP86F409NG 15.6.2 flash memory writing mode (operation command: 30h) table 15-8 shows flash memory writing mode process. note 1: ?xxh
page 156 15. serial prom mode 15.6 operation mode TMP86F409NG description of the flash memory writing mode 1. the 1st byte of the received data contains the ma tching data. when the serial prom mode is acti- vated, TMP86F409NG (hereafter called device), waits to receive the matching data (5ah). upon reception of the matching data, the device automatically adjusts the uart?s initial baud rate to 9600 bps. 2. when receiving the matching data (5ah), the device transmits an ech o back data (5ah) as the second byte data to the external controller. if the devi ce can not recognize the matching data, it does not transmit the echo back data and waits for the matc hing data again with automatic baud rate adjust- ment. therefore, the external cont roller should transmit the matching data repeatedly till the device transmits an echo back data. the transmission repe tition count varies depending on the frequency of device. for details, refer to table 15-5. 3. the 3rd byte of the received data contains the baud ra te modification data. the five types of baud rate modification data shown in table 15-4 are available. even if baud rate is not modified, the external controller should transmit the initial baud rate data (28h: 9600 bps). 4. only when the 3rd byte of the received data contai ns the baud rate modificat ion data corresponding to the device's operating frequency, th e device echoes back data the valu e which is the same data in the 4th byte position of the received data. after the ech o back data is transmitted, baud rate modification becomes effective. if the 3rd byte of the received data does not co ntain the baud rate modification data, the device enters the halts condition after se nding 3 bytes of baud rate modification error code (62h). 5. the 5th byte of the received data contains the command data (30h) to write the flash memory. 6. when the 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, 30h). if the 5th byte of the received da ta does not contain the op eration command data, the device enters the halt condition after sending 3 bytes of the operation command error code (63h). 7. the 7th byte contains the data for 15 to 8 bits of the password count storage address. when the data received with the 7th byte has no receiving error, the device does not send any data. if a receiving error or password error occurs, the device does not send any data and enters the halt condition. 8. the 9th byte contains the data for 7 to 0 bits of the password count storage address. when the data received with the 9th byte has no receiving error, the device does not send any data. if a receiving error or password error occurs, the device does not send any data and enters the halt condition. 9. the 11th byte contains the data for 15 to 8 bits of the password comparison start address. when the data received with the 11th byte has no receiving erro r, the device does not send any data. if a receiv- ing error or password error occurs, the device does not send any data and enters the halt condition. 10. the 13th byte contains the data for 7 to 0 bits of the password comparison start address. when the data received with the 13th byte ha s no receiving error, the device does not send any data. if a receiv- ing error or password error occurs, the device does not send any data and enters the halt condition. 11. the 15th through m?th bytes contain the passwor d data. the number of passwords becomes the data (n) stored in the password count storage address. the external password data is compared with n- byte data from the address specified by the passwor d comparison start addre ss. the external control- ler should send n-byte password data to the device. if the passwords do not match, the device enters the halt condition without returning an error code to the external controller . if the addresses from ffe0h to ffffh are filled with ?f fh?, the passwords are not conpare d because the device is consid- ered as a blank product. 12. the m?th + 1 through n?th - 2 bytes of the receive d data contain the binary data in the intel hex for- mat. no received data is echoed back to the extern al controller. after receiv ing the start mark (3ah for ?:?) in the intel hex format, the device starts data record reception. ther efore, the received data except 3ah is ignored until the start mark is received. afte r receiving the start mark, the device receives the data record, that consists of data lengt h, address, reco rd type, write data and checksum. since the device starts checksum cal culation after receiving an end r ecord, the external controller should wait for the checksum afte r sending the end record. if a recei ving error or intel hex format error occurs, the device enters the halts condition without returning an error code to the external con- troller. 13. the n?th - 1 and n?th bytes contain the checksum upper and lower bytes. for details on how to calcu- late the sum, refer to " 15.8 checksum (sum) ". the checksum is calculated only when the end record is detected and no receivi ng error or intel hex format er ror occurs. after sending the end
page 157 TMP86F409NG record, the external controller ju dges whether the transmission is co mpleted correctly by receiving the checksum sent by the device. 14. after transmitting the checksu m, the device waits for the next operation command data. note 1: do not write only the address from ffe0h to ffffh when all flash memory data is the same. if only these area are written, the subsequent operation can not be executed due to password error. note 2: to rewrite data to flash memory addresses at whic h data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data.
page 158 15. serial prom mode 15.6 operation mode TMP86F409NG 15.6.3 ram loader mode (o peration command: 60h) table 15-9 shows ram loader mode process. note 1: ?xxh
page 159 TMP86F409NG note 8: if an error occurs during the reception of a password address or a password string, TMP86F409NG stops uart commu- nication and enters the halt condition. in th is case, initialize TMP86F409NG by the reset pin and reactivate the serial prom mode. description of ram loader mode 1. the 1st through 4th bytes of the transmitted and recei ved data contains the same data as in the flash memory writing mode. 2. in the 5th byte of the received data contains the ram loader command data (60h). 3. when th 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position (in this case, 60h). if the 5th byte does not contain the operation command data, the device enters the halt condition after send- ing 3 bytes of operation command error code (63h). 4. the 7th through m?th bytes of the transmitted and received data contai n the same data as in the flash memory writing mode. 5. the m?th + 1 through n?th - 2 bytes of the received data contain the binary data in the intel hex for- mat. no received data is echoed back to the extern al controller. after receiv ing the start mark (3ah for ?:?) in the intel hex format, the device starts data record reception. ther efore, the received data except 3ah is ignored until the start mark is received. afte r receiving the start mark, the device receives the data record, that consists of data lengt h, address, reco rd type, write data and checksum. the writing data of the data record is written in to ram specified by address. since the device starts checksum calculation after receiving an end record, the external contro ller should wait for the check- sum after sending the end record. if a receiving error or intel hex format error occurs, the device enters the halts condition without returning an error code to the external controller. 6. the n?th - 1 and n?th bytes contain the checksum upper and lower bytes. for details on how to calcu- late the sum, refer to " 15.8 checksum (sum) ". the checksum is calculated only when the end record is detected and no receivi ng error or intel hex format er ror occurs. after sending the end record, the external controller ju dges whether the transmission is co mpleted correctly by receiving the checksum sent by the device. 7. after transmitting the checksum to the external controller, the boot program jumps to the ram address that is specified by the first received data record. note 1: to rewrite data to flash memory addresses at whic h data (including ffh) is already written, make sure to erase the existing data by "sector erase" or "chip erase" before rewriting data.
page 160 15. serial prom mode 15.6 operation mode TMP86F409NG 15.6.4 flash memory sum out put mode (operati on command: 90h) table 15-10 shows flash memory sum output mode process. note 1: ?xxh description of the flash memory sum output mode 1. the 1st through 4th bytes of the transmitted and recei ved data contains the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the command data in the flash memory sum output mode (90h). 3. when the 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, 90h). if the 5th byte of the received da ta does not contain the op eration command data, the device enters the halt condition after transmitting 3 bytes of operation command error code (63h). 4. the 7th and the 8th bytes contain the upper and lowe r bits of the checksum, respectively. for how to calculate the checksum, refer to " 15.8 checksum (sum) ". 5. after sending the checksum, the device waits for the next operation command data. table 15-10 flash memo ry sum output process transfer bytes transfer data from external control- ler to TMP86F409NG baud rate transfer data from TMP86F409NG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h
page 161 TMP86F409NG 15.6.5 product id code output mode (operation command: c0h) table 15-11 shows product id code output mode process. note: ?xxh description of product id code output mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the product id code output mode command data (c0h). 3. when the 5th byte contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte positio n of the received data (i n this case, c0h). if the 5th byte data does not contain the operation command data, the device enters the halt condition after sending 3 bytes of operation command error code (63h). 4. the 9th through 19th bytes contain the product id code. for details, refer to " 15.11 product id code ". table 15-11 product id code output process transfer bytes transfer data from external controller to TMP86F409NG baud rate transfer data from TMP86F409NG to external controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h
page 162 15. serial prom mode 15.6 operation mode TMP86F409NG 5. after sending the checksum, the device waits for the next operation command data.
page 163 TMP86F409NG 15.6.6 flash memory status out put mode (operati on command: c3h) table 15-12 shows flash memory status output mode process. note 1: ?xxh description of flash memory status output mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the flash memory status output mode command data (c3h). 3. when the 5th byte contains the operation command data shown in table 15-6, the device echoes back the value which is the same data in the 6th byte positio n of the received data (i n this case, c3h). if the 5th byte does not contain the operation command data, the device enters the halt condition after send- ing 3 bytes of operation command error code (63h). 4. the 9th through 13th bytes contain the status code. for details on the status code, refer to " 15.12 flash memory status code ". 5. after sending the status code, the device wa its for the next operation command data. table 15-12 flash memory status output mode process transfer bytes transfer data from external con- troller to TMP86F409NG baud rate transfer data from TMP86F409NG to exter- nal controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h
page 164 15. serial prom mode 15.6 operation mode TMP86F409NG 15.6.7 flash memory read protection setting mode (operation command: fah) table 15-13 shows flash memory read protection setting mode process. note 1: ?xxh description of the flash memory read protection setting mode 1. the 1st through 4th bytes of the transmitted and r eceived data contain the same data as in the flash memory writing mode. 2. the 5th byte of the received data contains the command data in th e flash memory status output mode (fah). 3. when the 5th byte of the received data contains the operation command data shown in table 1-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in table 15-13 flash memory read protection setting mode process transfer bytes transfer data from external con- troller to TMP86F409NG baud rate transfer data from TMP86F409NG to exter- nal controller boot rom 1st byte 2nd byte matching data (5ah) - 9600 bps 9600 bps - (automatic baud rate adjustment) ok: echo back data (5ah) error: nothing transmitted 3rd byte 4th byte baud rate modification data (see table 15-4) - 9600 bps 9600 bps - ok: echo back data error: a1h
page 165 TMP86F409NG this case, fah). if the 5th byte does not contai n the operation command data, the device enters the halt condition after transmitting 3 bytes of operation command error code (63h). 4. the 7th through m?th bytes of the transmitted and received data contai n the same data as in the flash memory writing mode. 5. the n'th byte contains the status to be transmitted to the external controller in the case of the success- ful read protection.
page 166 15. serial prom mode 15.7 error code TMP86F409NG 15.7 error code when detecting an error, the device tr ansmits the error code to the external controller, as shown in table 15-14. note: if a password error occurs, TMP86F409NG does not transmit an error code. 15.8 checksum (sum) 15.8.1 calculation method the checksum (sum) is calculated with the sum of all bytes, and the obtain ed result is returned as a word. the data is read for each byte unit and th e calculated result is returned as a word. example: the checksum which is transmitted by executing the fl ash memory write comman d, ram loader command, or flash memory sum output command is calculated in the manner, as shown above. table 15-14 error code transmit data meaning of error data 62h, 62h, 62h baud rate modification error. 63h, 63h, 63h operation command error. a1h, a1h, a1h framing error in the received data. a3h, a3h, a3h overrun error in the received data. a1h if the data to be calculated consists of the four bytes, the checksum of the data is as shown below. b2h a1h + b2h + c3h + d4h = 02eah sum (high)= 02h sum (low)= eah c3h d4h
page 167 TMP86F409NG 15.8.2 calculation data the data used to calculate the ch ecksum is listed in table 15-15. table 15-15 checksum calculation data operating mode calculation data description flash memory writing mode data in the entire area of the flash memory even when a part of the flash memory is written, the checksum of the entire flash memory area (f000h to fffh) is calculated. the data length, address, record type and checksum in intel hex format are not included in the checksum. flash memory sum output mode ram loader mode ram data written in the first received ram address through the last received ram address the length of data, address, record type and checksum in intel hex format are not included in the checksum. product id code output mode 9th through 18th bytes of the transferred data for details, refer to " 15.11 product id code ". flash memory status output mode 9th through 12th bytes of the tran sferred data for details, refer to " 15.12 flash memory status code " flash memory erasing mode all data in the erased area of the flash memory (the whole or part of the flash memory) when the sector erase is exec uted, only the erased area is used to calculate the checksum. in the case of the chip erase, an entire area of the flash memory is used.
page 168 15. serial prom mode 15.9 intel hex format (binary) TMP86F409NG 15.9 intel hex format (binary) 1. after receiving the checksum of a data record, the device waits for the start mark (3ah ?:?) of the next data record. after receiving the checksum of a data reco rd, the device ignores the data except 3ah transmitted by the external controller. 2. after transmitting the checksum of en d record, the external controller mu st transmit nothing, and wait for the 2-byte receive data (upper and lower bytes of the checksum). 3. if a receiving error or intel hex fo rmat error occurs, the device enters the halt condition without returning an error code to the external controller. the in tel hex format error occurs in the following case: when the record type is not 00h, 01h, or 02h when a checksum error occurs when the data length of an extended record (record type = 02h) is not 02h when the device receives the data reco rd after receiving an extended record (record type = 02h ) with extended address of 1000h or larger. when the data length of the end record (record type = 01h) is not 00h 15.10passwords the consecutive eight or mo re-byte data in the flash memory ar ea can be specified to the password. TMP86F409NG compares the data string specified to the password with the password string transmitted from the external controller. the area in which passwords can be sp ecified is located at addre sses f000h to ff9fh. the area from ffa0h to ffffh can not be specified as the passwords area. if addresses from ffe0h through fff fh are filled with ?ffh?, the passw ords are not compared because the product is considered as a blank product. even in this case, the password count stor age addresses and password comparison start address must be specified. table 15-16 shows the password setting in the blank product and non- blank product. note 1: when addresses from ffe0h through ffffh are filled wi th ?ffh?, the product is re cognized as a blank product. note 2: the data including the same consecutive data (three or mo re bytes) can not be used as a password. (this causes a pass- word error data. TMP86F409NG transmits no data and enters the halt condition.) note 3: *: don?t care. note 4: when the above condition is not met, a password error oc curs. if a password error occurs , the device enters the halt con - dition without returning the error code. note 5: in the flash memory writing mode or ram loader mode, the blank product receives the intel hex format data immediately after receiving pcsa without receiving password strings. in this case, the subsequent processing is performed correctly because the blank product ignores the data exc ept the start mark (3ah ?:?) as the intel hex format data, even if the exter- nal controller transmits the dummy password string. however, if the dummy password string contains ?3ah?, it is detected as the start mark erroneously. the micr ocontroller enters the halt mode. if this causes the problem, do not transmit the dummy password strings. note 6: in the flash memory erasing mode, t he external controller must not transmit the password string for the blank product. table 15-16 password setting in the blank product and non-blank product password blank product (note 1) non-blank product pnsa (password count storage address) f000h
page 169 TMP86F409NG figure 15-5 password comparison 15.10.1password string the password string transmitted from th e external controller is compared w ith the specified data in the flash memory. when the password string is not matched to the data in the flash memory, the device enters the halt condition due to the password error. 15.10.2handling of password error if a password error occurs, the device enters the halt c ondition. in this case, reset the device to reactivate the serial prom mode. 15.10.3password management during program development if a program is modified many times in the development stage, confusion may arise as to the password. therefore, it is recommended to use a fixed password in the program development stage. example :specify pnsa to f000h, and the pa ssword string to 8 bytes from address f001h (pcsa becomes f001h.) password section code abs = 0f000h db 08h : pnsa definition db ?code1234? : password string definition 08h 01h 02h 03h 04h 05h 08h f012h f107h f108h flash memory f109h f10ah f10bh f10ch uart f0h 12h f1h 07h 01h 02h 03h 04h 05h 06h 07h 08h pnsa pcsa password string 06h 07h f10dh f10eh "08h" becomes the umber of passwords 8 bytes compare example pnsa = f012h pcsa = f107h password string = 01h,02h,03h,04h,05h 06h,07h,08h rxd pin
page 170 15. serial prom mode 15.11 product id code TMP86F409NG 15.11product id code the product id code is the 13-byte data containing the start address and the end address of rom. table 15-17 shows the product id code format. 15.12flash memory status code the flash memory status code is the 7-byte data including the read protection status and the status of the data from ffe0h to ffffh. table 15-18 shows the flash memory status code. table 15-17 product id code format data description in the case of TMP86F409NG 1st start mark (3ah) 3ah 2nd the number of transfer data (10 bytes from 3rd to 12th byte) 0ah 3rd address length (2 bytes) 02h 4th reserved data 1dh 5th reserved data 00h 6th reserved data 00h 7th reserved data 00h 8th rom block count 01h 9th the first address of rom (upper byte) f0h 10th the first address of rom (lower byte) 00h 11th the end address of rom (upper byte) ffh 12th the end address of rom (lower byte) ffh 13th checksum of the transferred data (2?s compliment for the sum of 3rd through 12th bytes) f2h table 15-18 flash memory status code data description in the case of TMP86F409NG 1st start mark 3ah 2nd transferred data count (3rd through 6th byte) 04h 3rd status code 00h to 03h (see figure below) 4th reserved data 00h 5th reserved data 00h 6th reserved data 00h 7th checksum of the transferred data (2?s compliment for the sum of 3rd through 6th data) 3rd byte 00h 01h 02h 03h checksum 00h ffh feh fdh status code 1 76543210 rpena blank (initial value: 0000 00**)
page 171 TMP86F409NG some operation commands are limited by the flash memory stat us code 1. if the read pr otection is enabled, flash memory writing mode command and ram loader mode co mmand can not be executed. erase all flash memory before executing these command. note: m : the command can be executed. pass: the command can be executed with a password. mmmmmm mmm pass pass 10 mmmm mmm pass
page 172 15. serial prom mode 15.13 specifying the erasure area TMP86F409NG 15.13specifying the erasure area in the flash memory erasing m ode, the erasure area of the flas h memory is specified by n ? 2 byte data. the start address of an erasure area is specified by erasta, and the end address is specified by eraend. if erasta is equal to or smaller than eraend, the sector erase (erasure in 4 kbyte units) is executed. executing the sector erase while the read protection is enabled results in an infinite loop. if erasta is larger than eraend, th e chip erase (erasure of an entire flash memory area) is executed and the read protection is disabled. therefore, execute the chip erase (not sector erase) to disable the read protection. note: when the sector erase is executed for the area cont aining no flash cell, TMP86F409NG stops the uart communi- cation and enters the halt condition. 15.14port input control register in the serial prom mode, the input level is fixed to the all ports except p03 and p02 ports with a hardware feature to prevent overlap current to unused ports. (all port inpu ts and peripheral function inputs shared with the ports become invalid.) therefore, to access to the flash memory in the ram load er mode without uart communication, port inputs must be valid. to make port inputs valid, set the pin of the port input contro l register (spcr) to ?1?. the spcr register is not operated in the mcu mode. erasure area specification data (n ?
page 173 TMP86F409NG note 1: the spcr register can be read or written only in the seri al prom mode. when the write instruction is executed to the spcr register in the mcu mode, the port input control can not be performed. when the read instruction is executed for the spcr register in the mcu mode, read data of bit7 to 1 are unstable. note 2: all i/o ports except p03 and p02 po rts are controlled by the spcr register. port input control register spcr (0feah) 76543210 pin (initial value: **** ***0) pin port input control in the serial prom mode 0 : invalid port inputs (the input level is fixed with a hardware feature.) 1 : valid port inputs r/w
page 174 15. serial prom mode 15.15 flowchart TMP86F409NG 15.15flowchart start setup receive uart data receive data = 5ah adjust the baud rate (adjust the source clock to 9600 bps) no yes transmit uart data (transmit data = 5ah) receive uart data modify the baud rate based on the receive data receive data = 30h (flash memory writing mode) receive data = 60h (ram loader mode) receive uart data (intel hex format) transmit uart data (checksum of an entire area) receive uart data transmit uart data (transmit data = 60h) receive uart data (intel hex format) jump to the start address of ram program transmit uart data (checksum of an entire area) receive data = c0h (product id code output mode) transmit uart data (transmit data = c0h) flash memory write process ram write process transmit uart data (product id code) transmit uart data (echo back the baud rate modification data) verify the password (compare the receive data and flash memory data) read protection check protection disabled read protection check protection disabled infinite loop infinite loop ng protection enable ng receive data = c3h (flash memory status output mode) transmit uart data (transmit data = c3h) receive data = f0h (flash memory erasing mode) transmit uart data (transmit data = f0h) infinite loop ng chip erase (erase on entire area) transmit uart data (checksum of an entire area) receive data = fah (read protection setting mode) transmit uart data (transmit data = fah) read protection setting read protection check blank product check infinite loop ng blank product check blank product check non-blank product non-blank product ok blank product ok blank product check non-blank product ok ok blank product check non-blank product blank product protection enable blank product disable read protection blank product receive uart data receive data sector erase (block erase) upper 4 bits x 1000h to lower 4 bits x 1000h transmit uart data (checksum of the erased area) upper 4 bits > lower 4 bits transmit uart data (transmit data = 30h) transmit uart data (transmit data = 90h) receive data = 90h (flash memory sum output mode) verify the password (compare the receive data and flash memory data) transmit uart data (checksum) verify the password (compare the receive data and flash memory data) verify the password (compare the receive data and flash memory data) transmit uart data (status of the read protection and blank product) transmit uart data (transmit data = fbh) read protection check upper 4 bits < lower 4 bits protection enabled infinite loop protection disabled
page 175 TMP86F409NG 15.16uart timing table 15-19 uart timing-1 (vdd = 4.5 to 5.5 v, fc = 2 to 16 mhz, topr = -10 to 40c) parameter symbol clock frequency (fc) minimum required time at fc = 2 mhz at fc = 16 mhz time from matching data reception to the echo back cmeb1 approx. 930 465 reset pin rxd pin rxsup (5ah) cmeb1 (5ah) cmtr2 (28h) (28h) cmeb2 cmtr3 (30h) (30h) cmeb3 cmtr4 txd pin rxd pin txd pin (5ah) (5ah) (5ah) cmtr1
page 176 15. serial prom mode 15.16 uart timing TMP86F409NG
page 177 TMP86F409NG 16. input/output circuitry 16.1 control pins the input/output circuitries of the TMP86F409NG control pins are shown below. note: the test pin of tmp86fh09/f809/f409ng does not have a pull-down resistor and diode(d1). fix the test pin at low level in mcu mode. control pin i/o input/output circuitry remarks xin xout input output resonator connecting pins r f = 1.55 m ? ? ? ? ? ? ? fc rf r o osc.enable xin xout vdd vdd fs rf r o osc.enable xtin xten xtout vdd vdd r in r vdd address trap reset watchdog timer reset system clock reset r
page 178 16. input/output circuitry 16.2 input/output ports TMP86F409NG 16.2 input/output ports note: input status on pins set for input mode are read in into the internal circuit. therefore, when using the ports in a maxtur e of input and output modes, the contents of the output latches for t he ports that are set for input mode may be rewritten by exe- cution of bit manipulating instructions. control pin i/o input/output circuitry remarks p0 i/o sink open drain output or push-pull output hysteresis input high current output(nch) (programmable port option) p1 i/o tri-state i/o hysteresis input p2 i/o sink open drain output hysteresis input p3 i/o tri-state i/o hysteresis input or cmos input initial "high-z" high-z control vdd r pch control data output input from output latch pin input initial "high-z" disable vdd r data output pin input initial "high-z" vdd r data output input from output latch pin input initial "high-z" disable vdd r data output pin input key on wake up input initial "high-z" disable vdd r data output pin input p33,32 initial "high-z" disable vdd r data output pin input p31,30 p37 to 34 analog input analog input
page 179 TMP86F409NG 17. electrical characteristics 17.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operat ion, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rati ng is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or explode resul ting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximu m rating value will ever be exceeded. (vss = 0 v) parameter symbol pins ratings unit supply voltage v dd -0.3 to 6.0 v input voltage v in -0.3 to v dd + 0.3 v output voltage v out1 -0.3 to v dd + 0.3 v output current (per 1 pin) i out1 p0, p1, p3 ports -1.8 ma i out2 p1, p2, p3 ports 3.2 i out3 p0 ports 30 output current (total)
page 180 17. electrical characteristics 17.2 operating conditions TMP86F409NG 17.2 operating conditions the operating conditions show the conditions under which the device be used in orde r for it to operate normally while maintaining its quality. if the device is used outsid e the range of operating conditions (power supply voltage, operating temperature range, or ac/dc rated values), it may operate erraticially. therefore, when designing your application equipment, always make sure its intended working conditio ns will not exceed th e range of operating conditions. 17.2.1 mcu mode
page 181 TMP86F409NG 17.2.3 serial prom mode (v ss = 0 v, topr = -10 to 40
page 182 17. electrical characteristics 17.3 dc characteristics TMP86F409NG 17.3 dc characteristics note 1: typical values show those at topr = 25 ? n program coutner (pc) n+1 n+2 n+3 1 machine cycle (4/fc or 4/fs) mcu current i [ma] ddp-p typ. current momentary flash current max. current sum of average momentary flash current and mcu current
page 183 TMP86F409NG 17.4 ad characteristics note 1: the total error includes all errors except a quanitization error, and is defined as a maximum deviation from the ideal c on- version line. note 2: conversion time is defferent in recommended value by power supply voltage. note 3: the voltage to be input on the ain input pin must not exceed the range between v dd and v ss . if a voltage outside this range is input, conversion values will become unstable and conversion values of other channels will also be affected. note 4: the operating temperature(topr) must not exceed the range between -20 to 85
page 184 17. electrical characteristics 17.5 ac characteristics TMP86F409NG 17.5 ac characteristics note 1: the operating temperature(topr) must not exceed the range between -20 to 85
page 185 TMP86F409NG 17.7 recommended osc illating conditions note 1: to ensure stable oscillation, the re sonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. note 2: the product numbers and specifications of the resonators by murata manufacturing co., ltd. are subject to change. for up-to-date information, please refer to the following url: http://www.murata.com 17.8 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming - when using the device (oscillator) in plac es exposed to high electric fields such as cathode-ray tubes, we recommend elec- trically shielding the package in order to maintain normal operating condition. xtin xtout (2) low-frequency oscillation xin xout c 1 c 2 (1) high-frequency oscillation c 1 c 2
page 186 17. electrical characteristics 17.8 handling precaution TMP86F409NG
page 187 TMP86F409NG 18. package dimensions sdip32-p-400-1.78 rev 01 unit: mm
page 188 18. package dimensions TMP86F409NG
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